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Chapter 22. Intel i860 Dependent Features

 mxp

Enable support for the i860XP instructions and control registers. By default, this option is dis 

abled so that only the base instruction set (i.e., i860XR) is supported.

 mintel syntax

The i860 assembler defaults to AT&T/SVR4 syntax. This option enables the Intel syntax.

22.3. i860 Machine Directives

.dual

Enter dual instruction mode. While this directive is supported, the preferred way to use dual

instruction mode is to explicitly code the dual bit with the

d.

prefix.

.enddual

Exit dual instruction mode. While this directive is supported, the preferred way to use dual in 

struction mode is to explicitly code the dual bit with the

d.

prefix.

.atmp

Change the temporary register used when expanding pseudo operations. The default register is

r31

.

The

.dual

,

.enddual

, and

.atmp

directives are available only in the Intel syntax mode.

Both syntaxes allow for the standard

.align

directive. However, the Intel syntax additionally allows

keywords for the alignment parameter: "

.align type

", where `type' is one of

.short

,

.long

,

.quad

,

.single

,

.double

representing alignments of 2, 4, 16, 4, and 8, respectively.

22.4. i860 Opcodes

All of the Intel i860XR and i860XP machine instructions are supported. Please see either i860 Micro 

processor Programmer's Reference Manual or i860 Microprocessor Architecture for more informa 

tion.

22.4.1. Other instruction support (pseudo instructions)

For compatibility with some other i860 assemblers, a number of pseudo instructions are supported.

While these are supported, they are a very undesirable feature that should be avoided   in partic 

ular, when they result in an expansion to multiple actual i860 instructions. Below are the pseudo 

instructions that result in expansions.

Load large immediate into general register:

The pseudo instruction

mov imm,%rn

(where the immediate does not fit within a signed 16 bit

field) will be expanded into:

orh large_imm@h,%r0,%rn

or large_imm@l,%rn,%rn

Load/store with relocatable address expression: