Chapter 21. 80386 Dependent Features

133

21.11. AT&T Syntax bugs

The UnixWare assembler, and probably other AT&T derived ix86 Unix assemblers, generate floating

point instructions with reversed source and destination registers in certain cases. Unfortunately, gcc

and possibly many other programs use this reversed syntax, so we're stuck with it.

For example

fsub %st,%st(3)

results in

%st(3)

being updated to

%st   %st(3)

rather than the expected

%st(3)   %st

. This

happens with all the non commutative arithmetic floating point operations with two register operands

where the source register is

%st

and the destination register is

%st(i)

.

21.12. Specifying CPU Architecture

as

may be told to assemble for a particular CPU architecture with the

.arch cpu_type

directive.

This directive enables a warning when gas detects an instruction that is not supported on the CPU

specified. The choices for

cpu_type

are:

i8086

i186

i286

i386

i486

i586

i686

pentium

pentiumpro

pentium4

k6

athlon

sledgehammer

Apart from the warning, there are only two other effects on

as

operation; Firstly, if you specify a CPU

other than

i486

, then shift by one instructions such as

sarl $1, %eax

will automatically use a two

byte opcode sequence. The larger three byte opcode sequence is used on the 486 (and when no archi 

tecture is specified) because it executes faster on the 486. Note that you can explicitly request the two

byte opcode by writing

sarl %eax

. Secondly, if you specify

i8086

,

i186

, or

i286

, and

.code16

or

.code16gcc

then byte offset conditional jumps will be promoted when necessary to a two instruction

sequence consisting of a conditional jump of the opposite sense around an unconditional jump to the

target.

Following the CPU architecture, you may specify

jumps

or

nojumps

to control automatic promotion

of conditional jumps.

jumps

is the default, and enables jump promotion; All external jumps will be

of the long variety, and file local jumps will be promoted as necessary. (Section 21.7 Handling of

Jump Instructions)

nojumps

leaves external conditional jumps as byte offset jumps, and warns about

file local conditional jumps that

as

promotes. Unconditional jumps are treated as for

jumps

.

For example

.arch i8086,nojumps

21.13. Notes

There is some trickery concerning the

mul

and

imul

instructions that deserves mention. The 16 ,

32 , 64  and 128 bit expanding multiplies (base opcode

0xf6

; extension 4 for

mul

and 5 for

imul

)

can be output only in the one operand form. Thus,

imul %ebx, %eax

does not select the expanding