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Chapter 21. 80386 Dependent Features

Integer constructors are

.word

,

.long

or

.int

, and

.quad

for the 16 , 32 , and 64 bit integer

formats. The corresponding instruction mnemonic suffixes are

s

(single),

l

(long), and

q

(quad).

As with the 80 bit real format, the 64 bit

q

format is only present in the

fildq

(load quad integer

to stack top) and

fistpq

(store quad integer and pop stack) instructions.

Register to register operations should not use instruction mnemonic suffixes.

fstl %st, %st(1)

will give a warning, and be assembled as if you wrote

fst %st, %st(1)

, since all register to register

operations use 80 bit floating point operands. (Contrast this with

fstl %st, mem

, which converts

%st

from 80 bit to 64 bit floating point format, then stores the result in the 4 byte location

mem

)

21.9. Intel's MMX and AMD's 3DNow! SIMD Operations

as

supports Intel's MMX instruction set (SIMD instructions for integer data), available on Intel's

Pentium MMX processors and Pentium II processors, AMD's K6 and K6 2 processors, Cyrix' M2

processor, and probably others. It also supports AMD's 3DNow! instruction set (SIMD instructions

for 32 bit floating point data) available on AMD's K6 2 processor and possibly others in the future.

Currently,

as

does not support Intel's floating point SIMD, Katmai (KNI).

The eight 64 bit MMX operands, also used by 3DNow!, are called

%mm0

,

%mm1

, ...

%mm7

. They contain

eight 8 bit integers, four 16 bit integers, two 32 bit integers, one 64 bit integer, or two 32 bit floating

point values. The MMX registers cannot be used at the same time as the floating point stack.

See Intel and AMD documentation, keeping in mind that the operand order in instructions is reversed

from the Intel syntax.

21.10. Writing 16 bit Code

While

as

normally writes only "pure" 32 bit i386 code or 64 bit x86 64 code depending on the default

configuration, it also supports writing code to run in real mode or in 16 bit protected mode code seg 

ments. To do this, put a

.code16

or

.code16gcc

directive before the assembly language instructions

to be run in 16 bit mode. You can switch

as

back to writing normal 32 bit code with the

.code32

directive.

.code16gcc

provides experimental support for generating 16 bit code from gcc, and differs from

.code16

in that

call

,

ret

,

enter

,

leave

,

push

,

pop

,

pusha

,

popa

,

pushf

, and

popf

instructions

default to 32 bit size. This is so that the stack pointer is manipulated in the same way over function

calls, allowing access to function parameters at the same stack offsets as in 32 bit mode.

.code16gcc

also automatically adds address size prefixes where necessary to use the 32 bit addressing modes that

gcc generates.

The code which

as

generates in 16 bit mode will not necessarily run on a 16 bit pre 80386 processor.

To write code that runs on such a processor, you must refrain from using any 32 bit constructs which

require

as

to output address or operand size prefixes.

Note that writing 16 bit code instructions by explicitly specifying a prefix or an instruction mnemonic

suffix within a 32 bit code section generates different machine instructions than those generated for a

16 bit code segment. In a 32 bit code section, the following code generates the machine opcode bytes

66 6a 04

, which pushes the value

4

onto the stack, decrementing

%esp

by 2.

pushw $4

The same code in a 16 bit code section would generate the machine opcode bytes

6a 04

(ie. without

the operand size prefix), which is correct since the processor default operand size is assumed to be 16

bits in a 16 bit code section.