Chapter 21.

80386 Dependent Features

The i386 version

as

supports both the original Intel 386 architecture in both 16 and 32 bit mode as

well as AMD x86 64 architecture extending the Intel architecture to 64 bits.

21.1. Options

The i386 version of

as

has a few machine dependent options:

 32 |  64

Select the word size, either 32 bits or 64 bits. Selecting 32 bit implies Intel i386 architecture,

while 64 bit implies AMD x86 64 architecture.

These options are only available with the ELF object file format, and require that the necessary

BFD support has been included (on a 32 bit platform you have to add  enable 64 bit bfd to

configure enable 64 bit usage and use x86 64 as target platform).

 n

By default, x86 GAS replaces multiple nop instructions used for alignment within code sections

with multi byte nop instructions such as leal 0(%esi,1),%esi. This switch disables the optimiza 

tion.

21.2. AT&T Syntax versus Intel Syntax

as

now supports assembly using Intel assembler syntax.

.intel_syntax

selects Intel mode, and

.att_syntax

switches back to the usual AT&T mode for compatibility with the output of

gcc

. Ei 

ther of these directives may have an optional argument,

prefix

, or

noprefix

specifying whether

registers require a

%

prefix. AT&T System V/386 assembler syntax is quite different from Intel syn 

tax. We mention these differences because almost all 80386 documents use Intel syntax. Notable

differences between the two syntaxes are:

AT&T immediate operands are preceded by

$

; Intel immediate operands are undelimited (Intel

push 4

is AT&T

pushl $4

). AT&T register operands are preceded by

%

; Intel register operands

are undelimited. AT&T absolute (as opposed to PC relative) jump/call operands are prefixed by

*

;

they are undelimited in Intel syntax.

AT&T and Intel syntax use the opposite order for source and destination operands. Intel

add eax,

4

is

addl $4, %eax

. The

source, dest

convention is maintained for compatibility with previ 

ous Unix assemblers. Note that instructions with more than one source operand, such as the

enter

instruction, do not have reversed order. Section 21.11 AT&T Syntax bugs.

In AT&T syntax the size of memory operands is determined from the last character of the instruction

mnemonic. Mnemonic suffixes of

b

,

w

,

l

and

q

specify byte (8 bit), word (16 bit), long (32 bit) and

quadruple word (64 bit) memory references. Intel syntax accomplishes this by prefixing memory

operands (not the instruction mnemonics) with

byte ptr

,

word ptr

,

dword ptr

and

qword

ptr

. Thus, Intel

mov al, byte ptr foo

is

movb foo, %al

in AT&T syntax.