14

Chapter 2. Overview

This option is currently supported only when the primary target

as

is configured for is a

mips ELF or ECOFF target. Furthermore, the primary target or others specified with

 enable targets=...

at configuration time must include support for the other format, if

both are to be available. For example, the Irix 5 configuration includes support for both.

Eventually, this option will support more configurations, with more fine grained control over the

assembler's behavior, and will be supported for more processors.

 nocpp

as

ignores this option. It is accepted for compatibility with the native tools.

 trap

 no trap

 break

 no break

Control how to deal with multiplication overflow and division by zero.

 trap

or

 no break

(which are synonyms) take a trap exception (and only work for Instruction Set Architecture level

2 and higher);

 break

or

 no trap

(also synonyms, and the default) take a break exception.

 n

When this option is used,

as

will issue a warning every time it generates a nop instruction from

a macro.

The following options are available when as is configured for an MCore processor.

 jsri2bsr

 nojsri2bsr

Enable or disable the JSRI to BSR transformation. By default this is enabled. The command line

option

 nojsri2bsr

can be used to disable it.

 sifilter

 nosifilter

Enable or disable the silicon filter behaviour. By default this is disabled. The default can be

overridden by the

 sifilter

command line option.

 relax

Alter jump instructions for long displacements.

 mcpu=[210|340]

Select the cpu type on the target hardware. This controls which instructions can be assembled.

 EB

Assemble for a big endian target.

 EL

Assemble for a little endian target.

See the info pages for documentation of the MMIX specific options.

The following options are available when as is configured for an Xtensa processor.

 density |  no density

Enable or disable use of instructions from the Xtensa code density option. This is enabled by

default when the Xtensa processor supports the code density option.